NEC N8101-732F Datenblatt Seite 160
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Intel® Xeon® Processor E5-2400 v2 Product Family 160
Datasheet Volume One
Processor Land Listing
DDR2_DQ[02] W39 SSTL I/O
DDR2_DQ[03] W38 SSTL I/O
DDR2_DQ[04] AD37 SSTL I/O
DDR2_DQ[05] AC37 SSTL I/O
DDR2_DQ[06] Y39 SSTL I/O
DDR2_DQ[07] Y38 SSTL I/O
DDR2_DQ[08] T39 SSTL I/O
DDR2_DQ[09] T38 SSTL I/O
DDR2_DQ[10] M38 SSTL I/O
DDR2_DQ[11] M39 SSTL I/O
DDR2_DQ[12] U39 SSTL I/O
DDR2_DQ[13] U38 SSTL I/O
DDR2_DQ[14] N39 SSTL I/O
DDR2_DQ[15] N38 SSTL I/O
DDR2_DQ[16] J38 SSTL I/O
DDR2_DQ[17] J39 SSTL I/O
DDR2_DQ[18] H36 SSTL I/O
DDR2_DQ[19] G36 SSTL I/O
DDR2_DQ[20] K38 SSTL I/O
DDR2_DQ[21] K39 SSTL I/O
DDR2_DQ[22] H37 SSTL I/O
DDR2_DQ[23] G37 SSTL I/O
DDR2_DQ[24] D39 SSTL I/O
DDR2_DQ[25] C39 SSTL I/O
DDR2_DQ[26] C37 SSTL I/O
DDR2_DQ[27] E37 SSTL I/O
DDR2_DQ[28] E38 SSTL I/O
DDR2_DQ[29] E39 SSTL I/O
DDR2_DQ[30] D37 SSTL I/O
DDR2_DQ[31] B37 SSTL I/O
DDR2_DQ[32] D9 SSTL I/O
DDR2_DQ[33] E9 SSTL I/O
DDR2_DQ[34] E5 SSTL I/O
DDR2_DQ[35] D5 SSTL I/O
DDR2_DQ[36] D10 SSTL I/O
DDR2_DQ[37] E10 SSTL I/O
DDR2_DQ[38] D6 SSTL I/O
DDR2_DQ[39] E6 SSTL I/O
Table 8-1. Land Name (Sheet 7 of 37)
Land Name
Land
Number
Buffer Type Direction
DDR2_DQ[40] G9 SSTL I/O
DDR2_DQ[41] H9 SSTL I/O
DDR2_DQ[42] G5 SSTL I/O
DDR2_DQ[43] H5 SSTL I/O
DDR2_DQ[44] G10 SSTL I/O
DDR2_DQ[45] H10 SSTL I/O
DDR2_DQ[46] G6 SSTL I/O
DDR2_DQ[47] H6 SSTL I/O
DDR2_DQ[48] P6 SSTL I/O
DDR2_DQ[49] P5 SSTL I/O
DDR2_DQ[50] V6 SSTL I/O
DDR2_DQ[51] V5 SSTL I/O
DDR2_DQ[52] N6 SSTL I/O
DDR2_DQ[53] N5 SSTL I/O
DDR2_DQ[54] U6 SSTL I/O
DDR2_DQ[55] U5 SSTL I/O
DDR2_DQ[56] AA6 SSTL I/O
DDR2_DQ[57] AA5 SSTL I/O
DDR2_DQ[58] AE6 SSTL I/O
DDR2_DQ[59] AE5 SSTL I/O
DDR2_DQ[60] Y6 SSTL I/O
DDR2_DQ[61] Y5 SSTL I/O
DDR2_DQ[62] AD6 SSTL I/O
DDR2_DQ[63] AD5 SSTL I/O
DDR2_DQS_DN[00] AA39 SSTL I/O
DDR2_DQS_DN[01] P39 SSTL I/O
DDR2_DQS_DN[02] G39 SSTL I/O
DDR2_DQS_DN[03] C38 SSTL I/O
DDR2_DQS_DN[04] D7 SSTL I/O
DDR2_DQS_DN[05] G7 SSTL I/O
DDR2_DQS_DN[06] T6 SSTL I/O
DDR2_DQS_DN[07] AC6 SSTL I/O
DDR2_DQS_DN[08] E31 SSTL I/O
DDR2_DQS_DN[09] AB38 SSTL I/O
DDR2_DQS_DN[10] R38 SSTL I/O
DDR2_DQS_DN[11] H38 SSTL I/O
DDR2_DQS_DN[12] A39 SSTL I/O
DDR2_DQS_DN[13] E8 SSTL I/O
Table 8-1. Land Name (Sheet 8 of 37)
Land Name
Land
Number
Buffer Type Direction
- Product Family 1
- Table of Contents 3
- Datasheet Volume One 10
- Revision History 11
- 1 Overview 13
- 1.1.2 Supported Technologies 14
- 1.2 Interfaces 15
- 1.2.2 PCI Express* 16
- Transaction 17
- Overview 18
- 1.3 Power Management Support 19
- 1.5 Package Summary 20
- 1.6 Terminology 20
- 1.7 Related Documents 22
- 1.9 State of Data 23
- 2 Interfaces 24
- 2.2 PCI Express* Interface 25
- 2.2.1.1 Transaction Layer 26
- 2.2.1.2 Data Link Layer 26
- 2.2.1.3 Physical Layer 26
- 2.3.1 DMI2 Error Flow 27
- 2.3.3 DMI2 Link Down 27
- Interfaces 28
- 2.5.1.1 Thermal Management 30
- 2.5.2.1 Ping() 30
- 2.5.2.2 GetDIB() 31
- Reserved 32
- # of Domains 32
- Byte# 5 32
- 2.5.2.3 GetTemp() 33
- 2.5.2.4 RdPkgConfig() 34
- 2.5.2.5 WrPkgConfig() 35
- DRAM Power Limit Performance 45
- CPU ID Data 48
- CPU code patch revision 49
- Current Config Limit Data 54
- RESERVED 54
- Accumulated Energy Status 55
- Accumulated CPU Energy 55
- Accumulated CPU Throttle Time 57
- 2.5.2.7 RdIAMSR() 59
- Cores 0,1.2...7 60
- Thread (0,1) Mask for Core4 60
- 2.5.2.8 RdPCIConfig() 63
- 2.5.2.9 RdPCIConfigLocal() 64
- DeviceBus Function Register 65
- 2.5.2.10 WrPCIConfigLocal() 66
- 2.5.3.1 Power-up Sequencing 68
- 2.5.3.2 Device Discovery 69
- 2.5.3.3 Client Addressing 69
- 2.5.3.4 C-states 70
- 2.5.3.5 S-states 71
- 2.5.3.6 Processor Reset 71
- 2.5.4 Multi-Domain Commands 73
- 2.5.5.1 Abort FCS 74
- 2.5.5.2 Completion Codes 74
- 2.5.7.1 Format 75
- 3 Technologies 77
- 3.1.2 Intel® VT-x Features 78
- 3.1.3 Intel® VT-d Objectives 78
- 3.2 Security Technologies 79
- 3.2.3 AES Instructions 80
- 3.3 Intel® Secure Key 81
- 3.4 Intel® OS Guard 81
- Technologies 82
- 4 Power Management 85
- Table 4-6. Intel® QPI States 87
- 4.2.2 Low-Power Idle States 88
- Processor Package State 89
- Core N State 89
- Core 0 State 89
- 4.2.4.1 Core C0 State 90
- 4.2.4.2 Core C1/C1E State 90
- 4.2.4.3 Core C3 State 91
- 4.2.4.4 Core C6 State 91
- 4.2.4.5 Delayed Deep C-States 91
- 4.2.5.1 Package C0 93
- 4.2.5.2 Package C1/C1E 93
- 4.2.5.3 Package C2 State 94
- 4.2.5.4 Package C3 State 94
- 4.2.5.5 Package C6 State 94
- 4.2.7 Processor P 95
- Power Specifications 95
- 4.3.1 CKE Power-Down 96
- 4.3.2 Self Refresh 96
- 4.3.2.1 Self Refresh Entry 97
- 4.3.2.2 Self Refresh Exit 97
- 4.3.2.3 DLL and PLL Shutdown 97
- 5 Thermal Management 98
- 5.1.5 Thermal Metrology 107
- ) Measurement Location 108
- 5.2.1 Processor Temperature 109
- 5.2.2.2 Clock Modulation 111
- 5.2.4 PROCHOT_N Signal 112
- 5.2.5 THERMTRIP_N Signal 112
- 6 Signal Descriptions 115
- 6.5 PECI Signal 118
- 6.7 JTAG and TAP Signals 119
- Miscellaneous Signals 119
- 7 Electrical Specifications 124
- BCLK{0/1}_DN) 125
- 7.1.6.1 PLL Power Supply 126
- 7.1.9.2 Decoupling Guidelines 127
- Electrical Specifications 128
- 7.2 Signal Group Summary 132
- 7.5 Mixing Processors 136
- 7.8 DC Specifications 138
- Figure 7-3. V 142
- 7.8.2 Die Voltage Validation 143
- Time [us] 144
- Unit Figure Notes 146
- O_ABS_MAX 149
- VHavg (mV) 150
- 250 + 0.5 (VHavg - 700) 150
- 550 + 0.5 (VHavg - 700) 150
- 7.9 Signal Quality 152
- 7.9.5.3 Activity Factor 154
- 1.3335 V 0.2835 V 3 ns 5 ns 155
- 1.2600 V 0.210 V 5 ns 5 ns 155
- 8 Processor Land Listing 157
- 8.2 Listing by Land Number 175
- 9 Package Mechanical 194
- Intel® Xeon® Processor E5 195
- 9.7 Processor Materials 199
- 9.8 Processor Markings 199
- 10.1 Introduction 200
- Solution) 201
- Keepout Zones 203
- Support (URS) 212
- °C. Meeting the processor’s 213
- 10.4 Boxed Processor Contents 216
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