Nec Network Controller uPD98502 Bedienungsanleitung PDF herunterladen (Seite 255)

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CHAPTER 4 ATM CELL PROCESSOR

Preliminary User’s Manual S15543EJ1V0UM

255

4.6 Initialization

This ATM Cell Processor is initialized by firmware that is based RISC instruction.

4.6.1 Before starting RISC core

RISC Core has 1 MB of Instruction space and 8 KB of physical Instruction RAM and 8 KB of instruction cache. The

Instruction space will be mapped to the external system memory space. Address of instruction space will be translated

by adding content of A_INBAR. V

4120A will set A_INBAR during initialization. Instruction memory space will be

placed in the system memory space to achieve faster instruction fetch. V

4120A has to transfer RISC Core F/W to the

assigned SDRAM area as well as its own S/W in its initialization, as shown in Figure 4-16. After transferring F/W, it

sets base address of RISC Core F/W in A_INBAR. At the same time, base address of shared memory space has to

be set in A_IBBAR. Then VR

4120A let ATM Cell Processor to start operation.

Figure 4-16. Transfer of F/W

PD98502 M/W &

RTOS

ATM Cell

Processing F/W

ROM Space

ATM Cell

Processing F/W

(copy)

2. RISC Core

fetches

instructions

1. transfers

F/W to

SDRAM

PD98502 M/W &

RTOS

(copy)

PD98502 Memory Space

SDRAM Space

1 2 ... 250 251 252 253 254 255 256 257 258 259 260 ... 594 595

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