Nec Network Controller uPD98502 Bedienungsanleitung

Preliminary User’s ManualµµµµPD98502Network ControllerDocument No. S15543EJ1V0UM00 (1st edition)Date Published December 2001 NS CP(K)

10Preliminary User’s Manual S15543EJ1V0UM3.4.15 SDRAM refresh...

CHAPTER 2 VR4120A100Preliminary User’s Manual S15543EJ1V0UM2.3.6 Program compatibilityThe VR4120A core is designed taking into consideration prog

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1012.4 Memory Management SystemThe VR4120A Core provides a memory management unit (MMU) w

CHAPTER 2 VR4120A102Preliminary User’s Manual S15543EJ1V0UM2.4.2 Virtual address spaceThis section describes the virtual/physical address space a

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1032.4.2.1 Virtual-to-physical address translationConverting a virtual address to a physi

CHAPTER 2 VR4120A104Preliminary User’s Manual S15543EJ1V0UM2.4.2.2 32-bit mode address translationFigure 2-26 shows the virtual-to-physical-addre

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1052.4.2.3 64-bit mode address translationFigure 2-27 shows the virtual-to-physical-addre

CHAPTER 2 VR4120A106Preliminary User’s Manual S15543EJ1V0UM2.4.2.4 Operating modesThe processor has three operating modes that function in both 3

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM107The User segment starts at address 0 and the current active user process resides in eit

CHAPTER 2 VR4120A108Preliminary User’s Manual S15543EJ1V0UM2.4.2.6 Supervisor-mode virtual addressingSupervisor mode shown in Figure 2-29 is desi

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM109Table 2-28. 32-bit and 64-bit Supervisor Mode SegmentsAddress Bit Status Register Bit

Preliminary User’s Manual S15543EJ1V0UM114.4.18 A_T1R (T1 Time Register)...

CHAPTER 2 VR4120A110Preliminary User’s Manual S15543EJ1V0UM2.4.2.7 Kernel-mode virtual addressingIf the Status register satisfies any of the foll

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM111Figure 2-30. Kernel Mode Address Space32-bit mode Note 10.5 Gbytes withTLB mapping0.5

CHAPTER 2 VR4120A112Preliminary User’s Manual S15543EJ1V0UMTable 2-29. 32-bit Kernel Mode SegmentsAddress Bit Status Register Bit Value Segment V

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM113(5) kseg3 (32-bit kernel mode, kernel space 3)When KX = 0 in the Status register and th

CHAPTER 2 VR4120A114Preliminary User’s Manual S15543EJ1V0UM(7) xksseg (64-bit kernel mode, current supervisor space)When KX = 1 in the Status regi

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM115(9) xkseg (64-bit kernel mode, physical spaces)When the KX = 1 in the Status register a

CHAPTER 2 VR4120A116Preliminary User’s Manual S15543EJ1V0UM2.4.3 Physical address spaceSo VR4120A core uses a 32-bit address, that the processor

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1172.4.4 System control coprocessorThe System Control Coprocessor (CP0) is implemented as

CHAPTER 2 VR4120A118Preliminary User’s Manual S15543EJ1V0UM2.4.4.1 Format of a TLB entryFigure 2-33 shows the TLB entry formats for both 32- and

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1192.4.5 CP0 registersThe CP0 registers explained below are accessed by the memory manage

12Preliminary User’s Manual S15543EJ1V0UM5.2.20 En_HT1 (Hash Table Register 1)...

CHAPTER 2 VR4120A120Preliminary User’s Manual S15543EJ1V0UM2.4.5.3 EntryLo0 (2) and EntryLo1 (3) registersThe EntryLo register consists of two re

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM121Table 2-32. Cache AlgorithmC Bit Value Cache Algorithm0 Cached1 Cached2 Uncached3 Cach

CHAPTER 2 VR4120A122Preliminary User’s Manual S15543EJ1V0UM2.4.5.5 Wired register (6)The Wired register is a read/write register that specifies t

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1232.4.5.6 EntryHi register (10)The EntryHi register is write-accessible. It is used to

CHAPTER 2 VR4120A124Preliminary User’s Manual S15543EJ1V0UM2.4.5.8 Config register (16)The Config register specifies various configuration option

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1252.4.5.9 Load linked address (LLAddr) register (17)The read/write Load Linked Address (

CHAPTER 2 VR4120A126Preliminary User’s Manual S15543EJ1V0UM2.4.5.11 Virtual-to-physical address translationDuring virtual-to-physical address tra

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM127Figure 2-46. TLB Address TranslationVirtual address (input)VPNandASIDExceptionExceptio

CHAPTER 2 VR4120A128Preliminary User’s Manual S15543EJ1V0UM2.4.5.13 TLB instructionsThe instructions used for TLB control are described below.(1)

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1292.5 Exception ProcessingThis chapter describes VR4120A CPU exception processing, incl

Preliminary User’s Manual S15543EJ1V0UM136.2.20 U_RP1IR (USB Rx Pool1 Information Register) ...

CHAPTER 2 VR4120A130Preliminary User’s Manual S15543EJ1V0UM2.5.2 Precision of exceptionsVR4120A CPU exceptions are logically precise; the instruc

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1312.5.3.1 Context register (4)The Context register is a read/write register containing t

CHAPTER 2 VR4120A132Preliminary User’s Manual S15543EJ1V0UM2.5.3.2 BadVAddr register (8)The Bad Virtual Address (BadVAddr) register is a read-onl

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1332.5.3.4 Compare register (11)The Compare register causes a timer interrupt; it maintai

CHAPTER 2 VR4120A134Preliminary User’s Manual S15543EJ1V0UM2.5.3.5 Status register (12)The Status register is a read/write register that contains

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM135Figure 2-52. Status Register Diagnostic Status Field1617181920212223240 BEV TS SR 0 CH

CHAPTER 2 VR4120A136Preliminary User’s Manual S15543EJ1V0UM(7) Status after resetThe contents of the Status register are undefined after Cold rese

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM137Table 2-35. Cause Register Exception Code FieldException Code Mnemonic Description0 In

CHAPTER 2 VR4120A138Preliminary User’s Manual S15543EJ1V0UM2.5.3.7 Exception program counter (EPC) register (14)The Exception Program Counter (EP

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1392.5.3.8 WatchLo (18) and WatchHi (19) registersThe VR4120A processor provides a debugg

14Preliminary User’s Manual S15543EJ1V0UMCHAPTER 7 PCI CONTROLLER ...

CHAPTER 2 VR4120A140Preliminary User’s Manual S15543EJ1V0UM2.5.3.9 XContext register (20)The read/write XContext register contains a pointer to a

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1412.5.3.11 Cache error register (27)The Cache Error register is a readable/writeable reg

CHAPTER 2 VR4120A142Preliminary User’s Manual S15543EJ1V0UM2.5.4 Details of exceptionsThis section describes causes, processes, and services of t

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM143Table 2-37. 32-Bit Mode Exception Vector Base AddressesVector Base Address (Virtual) V

CHAPTER 2 VR4120A144Preliminary User’s Manual S15543EJ1V0UM2.5.4.3 Priority of exceptionsWhile more than one exception can occur for a single ins

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1452.5.4.4 Cold reset exception(1) CauseThe Cold Reset exception occurs when the ColdRese

CHAPTER 2 VR4120A146Preliminary User’s Manual S15543EJ1V0UM2.5.4.5 Soft reset exception(1) CauseA Soft Reset (sometimes called Warm Reset) occurs

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1472.5.4.6 NMI exception(1) CauseThe Nonmaskable Interrupt (NMI) exception occurs when th

CHAPTER 2 VR4120A148Preliminary User’s Manual S15543EJ1V0UM2.5.4.7 Address error exception(1) CauseThe Address Error exception occurs when an att

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1492.5.4.8 TLB exceptionsThree types of TLB exceptions can occur:• TLB Refill exception o

Preliminary User’s Manual S15543EJ1V0UM158.3.4 UARTIER (UART Interrupt Enable Register)...

CHAPTER 2 VR4120A150Preliminary User’s Manual S15543EJ1V0UM(2) TLB invalid exception(a) CauseThe TLB Invalid exception occurs when the TLB entry t

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM151(3) TLB modified exception(a) CauseThe TLB Modified exception occurs when the TLB entry

CHAPTER 2 VR4120A152Preliminary User’s Manual S15543EJ1V0UM2.5.4.9 Bus error exception(1) CauseA Bus Error exception is raised by board-level cir

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1532.5.4.10 System call exception(1) CauseA System Call exception occurs during an attemp

CHAPTER 2 VR4120A154Preliminary User’s Manual S15543EJ1V0UM2.5.4.12 Coprocessor unusable exception(1) CauseThe Coprocessor Unusable exception occ

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1552.5.4.13 Reserved instruction exception(1) CauseThe Reserved Instruction exception occ

CHAPTER 2 VR4120A156Preliminary User’s Manual S15543EJ1V0UM2.5.4.14 Trap exception(1) CauseThe Trap exception occurs when a TGE, TGEU, TLT, TLTU,

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1572.5.4.16 Watch exception(1) CauseA Watch exception occurs when a load or store instruc

CHAPTER 2 VR4120A158Preliminary User’s Manual S15543EJ1V0UM2.5.4.17 Interrupt exception(1) CauseThe Interrupt exception occurs when one of the ei

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM159Figure 2-61. Common Exception Handling (1/2)(a) Handling Exceptions other than Cold Re

16Preliminary User’s Manual S15543EJ1V0UMLIST OF FIGURES (1/5)Figure No. Title Page1-1 Examples of the µPD98502 System Configuration ...

CHAPTER 2 VR4120A160Preliminary User’s Manual S15543EJ1V0UMFigure 2-61. Common Exception Handling (2/2)(b) Servicing Common Exceptions (Software)

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM161Figure 2-62. TLB/XTLB Refill Exception Handling (1/2)(a) Handling TLB/XTLB Refill Exc

CHAPTER 2 VR4120A162Preliminary User’s Manual S15543EJ1V0UMFigure 2-62. TLB/XTLB Refill Exception Handling (2/2)(b) Servicing TLB/XTLB Refill Ex

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM163Figure 2-63. Cold Reset Exception Handling(Hardware)PC←FFFF FFFF BFC0 0000H(Software)•

CHAPTER 2 VR4120A164Preliminary User’s Manual S15543EJ1V0UMFigure 2-64. Soft Reset and NMI Exception HandlingBD bit←1ErrorEPC←PC−4Set Status regi

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1652.6 Initialization InterfaceThis section describes the reset sequence of the VR4120A C

CHAPTER 2 VR4120A166Preliminary User’s Manual S15543EJ1V0UM2.6.3.1 Power modesThe VR4120A supports four power modes: Fullspeed mode, Standby mod

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1672.6.3.2 Privilege modeThe VR4120A supports three system modes: kernel expanded addres

CHAPTER 2 VR4120A168Preliminary User’s Manual S15543EJ1V0UM2.7 Cache MemoryThis section describes in detail the cache memory: its place in the V

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1692.7.2 Cache organizationThis section describes the organization of the on-chip data an

Preliminary User’s Manual S15543EJ1V0UM17LIST OF FIGURES (2/5)Figure No. Title Page2-29 Supervisor Mode Address Space ...

CHAPTER 2 VR4120A170Preliminary User’s Manual S15543EJ1V0UMFigure 2-67. Instruction Cache Line Format22 21VPTag0122Data0DataDataData31PTag : Phy

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1712.7.2.3 Accessing the cachesFigure 2-69 shows the virtual address (VA) index into the

CHAPTER 2 VR4120A172Preliminary User’s Manual S15543EJ1V0UM2.7.3.1 Cache write policyThe VR4120A Core manages its data cache by using a write-bac

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1732.7.5 Cache state transition diagramsThe following section describes the cache state d

CHAPTER 2 VR4120A174Preliminary User’s Manual S15543EJ1V0UM2.7.6 Cache data integrityFigures 2-72 to 2-86 shows checking operations for various c

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM175Figure 2-74. Data Check Flow on Store OperationsStartWrite-back andRefill (seeFigure 2

CHAPTER 2 VR4120A176Preliminary User’s Manual S15543EJ1V0UMFigure 2-76. Data Check Flow on Index_Writeback_Invalidate Operations= 0 (Clean)StartW

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM177Figure 2-78. Data Check Flow on Index_Store_Tag OperationsStartTag Writefrom TagLoENDF

CHAPTER 2 VR4120A178Preliminary User’s Manual S15543EJ1V0UMFigure 2-80. Data Check Flow on Hit_Invalidate OperationsStartValid bit ClearENDMiss o

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM179Figure 2-82. Data Check Flow on Fill OperationsStartRefill (seeFigure 2-85)ENDFigure 2

18Preliminary User’s Manual S15543EJ1V0UMLIST OF FIGURES (3/5)Figure No. Title Page2-71 Instruction Cache State Diagram ...

CHAPTER 2 VR4120A180Preliminary User’s Manual S15543EJ1V0UMFigure 2-84. Writeback FlowEOD ?YesNoWrite-backto memoryFigure 2-85. Refill FlowEOD ?

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM181Figure 2-86. Writeback & Refill FlowEOD ?YesNoWrite-backto memoryEOD ?Refill Start

CHAPTER 2 VR4120A182Preliminary User’s Manual S15543EJ1V0UM2.8 CPU Core InterruptsFour types of interrupt are available on the CPU core. These a

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM1832.8.5 Asserting interrupts2.8.5.1 Detecting hardware interruptsFigure 2-88 shows how

CHAPTER 2 VR4120A184Preliminary User’s Manual S15543EJ1V0UM2.8.5.2 Masking interrupt signalsFigure 2-89 shows the masking of the CPU core interru

Preliminary User’s Manual S15543EJ1V0UM185CHAPTER 3 SYSTEM CONTROLLER3.1 OverviewRegister mapThis block is an internal system controller for the

CHAPTER 3 SYSTEM CONTROLLER186Preliminary User’s Manual S15543EJ1V0UM• 66-MHz IBUS clock rate• Supports 266-MB/sec (32 bits @66 MHz) bursts on IBU

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM1873.1.9 System block diagramSystem ControllerIBUSSysADTIMERIBUS Master-IFFlash

CHAPTER 3 SYSTEM CONTROLLER188Preliminary User’s Manual S15543EJ1V0UM3.1.10 Data flow diagramVR4120A Core to SDRAM IBUS to SDRAMVR4120A Core to I

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM1893.2 Registers3.2.1 Register mapFollowing Table summarizes the controller’s

Preliminary User’s Manual S15543EJ1V0UM19LIST OF FIGURES (4/5)Figure No. Title Page4-19 Open_Channel Command and Indication...

CHAPTER 3 SYSTEM CONTROLLER190Preliminary User’s Manual S15543EJ1V0UMOffset Address Register Name R/W Access Description1000_00D8H MACAR1 R W/H/B

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM1913.2.2 S_GMR (General Mode Register)The general mode register “S_GMR” is a re

CHAPTER 3 SYSTEM CONTROLLER192Preliminary User’s Manual S15543EJ1V0UM3.2.4 S_ISR (Interrupt Status Register)The interrupt status register “S_ISR”

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM1933.2.5 S_IMR (Interrupt Mask Register)The interrupt mask register “S_IMR” is

CHAPTER 3 SYSTEM CONTROLLER194Preliminary User’s Manual S15543EJ1V0UM3.2.6 S_NSR (NMI Status Register)The interrupt status register “S_NSR” is a

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM1953.2.7 S_NER (NMI Enable Register)The NMI enable register “S_NER” is a read-w

CHAPTER 3 SYSTEM CONTROLLER196Preliminary User’s Manual S15543EJ1V0UM3.2.9 S_IOR (IO Port Register)The IO port register “S_IOR” is a read-write a

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM1973.2.10 S_WRCR (Warm Reset Control Register)The warm reset control register “

CHAPTER 3 SYSTEM CONTROLLER198Preliminary User’s Manual S15543EJ1V0UM3.2.11 S_WRSR (Warm Reset Status Register)The warm reset status register “S_

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM1993.2.12 S_PWCR (Power Control Register)The power control register “S_PWCR” is

Preliminary User’s Manual S15543EJ1V0UM2[MEMO]

20Preliminary User’s Manual S15543EJ1V0UMLIST OF FIGURES (5/5)Figure No. Title Page6-16 Data Receiving in EndPoint0, EndPoint6...

CHAPTER 3 SYSTEM CONTROLLER200Preliminary User’s Manual S15543EJ1V0UM3.2.13 S_PWSR (Power Status Register)The power status register “S_PWSR” is a

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2013.3 CPU InterfaceThe system controller provides the direct interface for the

CHAPTER 3 SYSTEM CONTROLLER202Preliminary User’s Manual S15543EJ1V0UMTable 3-1. Endian Configuration TableBIG pin ENDCENpinStatus registerRE fiel

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2033.3.6 I/O performanceThe following table indicates the I/O performance acces

CHAPTER 3 SYSTEM CONTROLLER204Preliminary User’s Manual S15543EJ1V0UM3.4 Memory InterfaceThe VR4120A accesses memory attached to the controller i

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2053.4.3 Memory signal connectionsµµµµPD98502SMD[31:0]SRMOE_BSRMCS_BSDRAS_BSDCS

CHAPTER 3 SYSTEM CONTROLLER206Preliminary User’s Manual S15543EJ1V0UM3.4.4 Memory performanceThe latency of memory accesses is determined by memo

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2073.4.5 RMMDR (ROM Mode Register)The ROM mode register “RMMDR” is a read-write

CHAPTER 3 SYSTEM CONTROLLER208Preliminary User’s Manual S15543EJ1V0UMinvalidSMASDCLKNormal ROM Read CycleSMDFAT(=4)SRMCS_BSRMOE_BSDWE_BHValid Read

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2093.4.7 SDMDR (SDRAM Mode Register)The SDRAM mode register “SDMDR” is a read-w

Preliminary User’s Manual S15543EJ1V0UM21LIST OF TABLES (1/2)Table No. Title Page2-1 System Control Coprocessor (CP0) Register Definitions...

CHAPTER 3 SYSTEM CONTROLLER210Preliminary User’s Manual S15543EJ1V0UM3.4.8 SDTSR (SDRAM Type Selection Register)The SDRAM type selection register

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2113.4.9 SDPTR (SDRAM Precharge Timing Register)The SDRAM precharge timing regi

CHAPTER 3 SYSTEM CONTROLLER212Preliminary User’s Manual S15543EJ1V0UM3.4.11 SDRCR (SDRAM Refresh Timer Count Register)The SDRAM refresh timer cou

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2133.4.13 Boot ROMThe system controller supports up to 8 MB of boot memory. Thi

CHAPTER 3 SYSTEM CONTROLLER214Preliminary User’s Manual S15543EJ1V0UMTable 3-7. Command Sequence(a) Program Command Sequence (4 Write Cycles)1st

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2153.4.1.4 Boot ROM signal connectionsSMD[31:0]SRMOE_BSDWE_BSRMCS_BExample (8 M

CHAPTER 3 SYSTEM CONTROLLER216Preliminary User’s Manual S15543EJ1V0UM3.4.14 SDRAM3.4.14.1 SDRAM address rangeSystem memory can be populated with

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2173.4.1.4 SDRAM word orderingFollowing table indicates the word-address order

CHAPTER 3 SYSTEM CONTROLLER218Preliminary User’s Manual S15543EJ1V0UMRAS_BSDCAS_BSMA[13:0]SMD[31:0]1 M x 16SDRAMA[11:0]DQ[15:0]RAS_BCS_BµPD98502(S

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2193.4.15 SDRAM refreshThe system controller supports CAS-Before-RAS (CBR) DRAM

22Preliminary User’s Manual S15543EJ1V0UMLIST OF TABLES (2/2)Table No. Title Page3-1 Endian Configuration Table...

CHAPTER 3 SYSTEM CONTROLLER220Preliminary User’s Manual S15543EJ1V0UM3.4.18 SDRAM memory initializationThe following sections describe the config

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2213.5 IBUS Interface3.5.1 Overview• IBUS Master and target capability• 64-wor

CHAPTER 3 SYSTEM CONTROLLER222Preliminary User’s Manual S15543EJ1V0UM31 07856341231 07856 34122 bytesOutline figure of Endian converter31 07856341

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2233.5.4 ITCNTR (IBUS Timeout Timer Control Register)The IBUS Timeout Timer con

CHAPTER 3 SYSTEM CONTROLLER224Preliminary User’s Manual S15543EJ1V0UM3.6 DSU (Deadman’s SW Unit)3.6.1 OverviewThe DSU detects when the VR4120A i

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2253.6.5 DSUTIMR (DSU Elapsed Time Register)This register indicates the elapsed

CHAPTER 3 SYSTEM CONTROLLER226Preliminary User’s Manual S15543EJ1V0UM3.7 Endian Mode Software Issues3.7.1 OverviewThe native endian mode for MIP

CHAPTER 3 SYSTEM CONTROLLERPreliminary User’s Manual S15543EJ1V0UM227Figure 3-1. Bit and Byte Order of Endian ModesBYTE0 BYTE1 BYTE2 BYTE3BYTE4 B

CHAPTER 3 SYSTEM CONTROLLER228Preliminary User’s Manual S15543EJ1V0UMHowever, when making half-word accesses into a data array consisting of word

Preliminary User’s Manual S15543EJ1V0UM229CHAPTER 4 ATM CELL PROCESSOR4.1 OverviewThis section describes functional specifications of ATM cell

Preliminary User’s Manual S15543EJ1V0UM23CHAPTER 1 INTRODUCTIONThe µPD98502 is a high performance controller, which can perform the protocol conve

CHAPTER 4 ATM CELL PROCESSOR230Preliminary User’s Manual S15543EJ1V0UM4.1.2 Block diagram of ATM cell processorFigure 4-1. Block Diagram of AT

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM2314.1.2.3 UTOPIA bus controllerThis block has some H/W resources – DMA cont

CHAPTER 4 ATM CELL PROCESSOR232Preliminary User’s Manual S15543EJ1V0UM4.1.2.4 Other blocksWork-RAM is 12 K-byte memory. Tables and Pool Descrip

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM2334.1.3.1 AAL-5 SAR sublayer functionWhen ATM Cell Processor transmits a ce

CHAPTER 4 ATM CELL PROCESSOR234Preliminary User’s Manual S15543EJ1V0UMFigure 4-4. ATM CellVCIGFCSegment48 byteVPIVPIPTIHECCLPheader12345678bitT

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM235(3) Cell schedulingATM Cell Processor uses Scheduling Table, Cell Timer an

CHAPTER 4 ATM CELL PROCESSOR236Preliminary User’s Manual S15543EJ1V0UM4.2 Memory SpaceAlthough the RISC Core in the ATM Cell Processor is a 32-

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM2374.2.1 Work RAM and register spaceWork RAM and Register Space are shown in

CHAPTER 4 ATM CELL PROCESSOR238Preliminary User’s Manual S15543EJ1V0UM4.4 Registers for ATM Cell ProcessingRegisters in ATM Cell Processor bloc

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM239Offset Address Register Name R/W Access Description1001_F0C8H A_TSR R/W W

CHAPTER 1 INTRODUCTION24Preliminary User’s Manual S15543EJ1V0UM1.3 System ConfigurationThe µPD98502 can perform bridging and routing function bet

CHAPTER 4 ATM CELL PROCESSOR240Preliminary User’s Manual S15543EJ1V0UM4.4.2 A_GMR (General Mode Register)A_GMR is used to select operation mode

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM2414.4.4 A_IMR (Interrupt Mask Register)A_IMR masks interruption for each co

CHAPTER 4 ATM CELL PROCESSOR242Preliminary User’s Manual S15543EJ1V0UM4.4.5 A_RQU (Receiving Queue Underrun Register)A_RQU shows the status of

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM2434.4.10 A_MSA0 to A_MSA3 (Mailbox Start Address Register)A_MSA0 to A_MSA3

CHAPTER 4 ATM CELL PROCESSOR244Preliminary User’s Manual S15543EJ1V0UM4.4.13 A_MWA0 to A_MWA3 (Mailbox Write Address Register)A_MWA0 to A_MWA3

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM2454.4.18 A_T1R (T1 Time Register)A_T1R shows time which user allows ATM Cel

CHAPTER 4 ATM CELL PROCESSOR246Preliminary User’s Manual S15543EJ1V0UM4.4.22 A_UMCMD (UTOPIA Management Interface Command Register)A_UMCMD sele

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM2474.5 Data StructureATM Cell Processor has Tx/Rx buffer structure similar t

CHAPTER 4 ATM CELL PROCESSOR248Preliminary User’s Manual S15543EJ1V0UMFigure 4-9. Tx Buffer Elements- Tx buffer directoryTx buffer directory Ad

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM2494.5.1.1 Packet descriptorA packet descriptor contains two words shown as

CHAPTER 1 INTRODUCTIONPreliminary User’s Manual S15543EJ1V0UM251.4 Block Diagram (Summary)Figure 1-2. Block Diagram of the µµµµPD98502SDRAMATM C

CHAPTER 4 ATM CELL PROCESSOR250Preliminary User’s Manual S15543EJ1V0UM4.5.1.2 Tx buffer directoryTx buffer directory contains some buffer descr

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM251Figure 4-12. Rx Pool StructureRx buffer desc.DataBufferDataBufferDataBuff

CHAPTER 4 ATM CELL PROCESSOR252Preliminary User’s Manual S15543EJ1V0UMFigure 4-13. Rx Pool Descriptor/Rx Buffer Directory/Rx Buffer Descriptor/

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM2534.5.2.1 Rx pool descriptorA pool descriptor contains two words shown as F

CHAPTER 4 ATM CELL PROCESSOR254Preliminary User’s Manual S15543EJ1V0UMFigure 4-15. Rx Buffer Descriptor/ Link Pointer-Rx link pointer-Rx buffer

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM2554.6 InitializationThis ATM Cell Processor is initialized by firmware that

CHAPTER 4 ATM CELL PROCESSOR256Preliminary User’s Manual S15543EJ1V0UM4.6.2 After RISC core’s F/W is startingRISC Core starts its operation fro

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM2574.7 CommandsHere, basic commands used in AAL-5 operation are described. O

CHAPTER 4 ATM CELL PROCESSOR258Preliminary User’s Manual S15543EJ1V0UM4.7.1 Set_Link_Rate commandThis command is used to set the link rate of A

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM2594.7.3 Close_Channel commandThe Close_Channel command is used to close a s

CHAPTER 1 INTRODUCTION26Preliminary User’s Manual S15543EJ1V0UM1.5 Block Diagram (Detail)1.5.1 VR4120A RISC processor coreWe will support real-t

CHAPTER 4 ATM CELL PROCESSOR260Preliminary User’s Manual S15543EJ1V0UM4.7.4 Tx_Ready commandThe Tx_Ready command is used by the VR4120A to noti

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM2614.7.5 Add_Buffers commandThe Add_Buffers command is used to add unused bu

CHAPTER 4 ATM CELL PROCESSOR262Preliminary User’s Manual S15543EJ1V0UM4.7.6 Indirect_Access commandThe Indirect_Access command is used to perfo

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM263Figure 4-24. Work RAM UsagePacket Info StructurePool(4 W ords x 64)Free B

CHAPTER 4 ATM CELL PROCESSOR264Preliminary User’s Manual S15543EJ1V0UM4.8.2.1 Transmission procedure(a) Setting transmitting dataBefore transmi

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM2654.8.2.2 Transmit queueTx_Ready command has to be issued in order to trans

CHAPTER 4 ATM CELL PROCESSOR266Preliminary User’s Manual S15543EJ1V0UM(2) Packet descriptorFigure 4-27. Transmit Queue Packet Descriptor10ENCCL

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM267(3) Tx VC tableFigure 4-28. Tx VC TableWord 0 V ENC CLPM PTI GFC IM C10AA

CHAPTER 4 ATM CELL PROCESSOR268Preliminary User’s Manual S15543EJ1V0UMWord0 Identical to the contents of Word0 in the packet descriptor in syste

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM269(2) Raw cell transmissionWhen host sends the non AAL-5 traffic packet whic

CHAPTER 1 INTRODUCTIONPreliminary User’s Manual S15543EJ1V0UM271.5.2 IBUSThe IBUS is a 32-bit, 66-MHz high-speed on-chip bus, which enables inter

CHAPTER 4 ATM CELL PROCESSOR270Preliminary User’s Manual S15543EJ1V0UM4.8.2.6 LLC encapsulationIf LLC encapsulation is indicated in Tx VC table

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM271(1) Rx VC tableFigure 4-32. Receive VC TableWord 0CLP BFA0 RID DD DP 0 CI

CHAPTER 4 ATM CELL PROCESSOR272Preliminary User’s Manual S15543EJ1V0UMCLP Set to a 1 if the CLP in the header of at least one cell of the packet

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM273Figure 4-33. Raw Cell Data FormatWORD0 CELL HEADERWORD1 BYTE2 BYTE1 BYTE0

CHAPTER 4 ATM CELL PROCESSOR274Preliminary User’s Manual S15543EJ1V0UMFigure 4-34. Receive Indication FormatUINFO PACKET SIZE31 16 15 0TIME STA

CHAPTER 4 ATM CELL PROCESSORPreliminary User’s Manual S15543EJ1V0UM275(2) Max No. of bytes violationThis error occurs if the last cell of a pack

CHAPTER 4 ATM CELL PROCESSOR276Preliminary User’s Manual S15543EJ1V0UM4.8.4 MailboxATM Cell Processor uses mailboxes as ring buffers in system

Preliminary User’s Manual S15543EJ1V0UM277CHAPTER 5 ETHERNET CONTROLLER5.1 OverviewThis section describes Ethernet Controller block. This Ethern

CHAPTER 5 ETHERNET CONTROLLER278Preliminary User’s Manual S15543EJ1V0UMFigure 5-1. Block Diagram of Ethernet ControllerTPO+TPO–TPI+TPI–Transceiv

CHAPTER 5 ETHERNET CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2795.2 RegistersRegisters of this block are categorized following four categ

CHAPTER 1 INTRODUCTION28Preliminary User’s Manual S15543EJ1V0UM1.5.3 System controllerSystem Controller is µPD98502’s internal system controller.

CHAPTER 5 ETHERNET CONTROLLER280Preliminary User’s Manual S15543EJ1V0UMOffset Address Register Name R/W Access Description1000_m0A8H:1000_m0C4HN/

CHAPTER 5 ETHERNET CONTROLLERPreliminary User’s Manual S15543EJ1V0UM281Table 5-3. Statistics Counter Register MapOffset Address Register Name R/

CHAPTER 5 ETHERNET CONTROLLER282Preliminary User’s Manual S15543EJ1V0UMOffset Address Register Name R/W Access Description1000_m1C4H En_TPCT R/W

CHAPTER 5 ETHERNET CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2835.2.1.3 DMA and FIFO management registersThese registers control to trans

CHAPTER 5 ETHERNET CONTROLLER284Preliminary User’s Manual S15543EJ1V0UM5.2.1.4 Interrupt and configuration registersThese register control inter

CHAPTER 5 ETHERNET CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2855.2.2 En_MACC1 (MAC Configuration Register 1)Bits Field R/W Default Descr

CHAPTER 5 ETHERNET CONTROLLER286Preliminary User’s Manual S15543EJ1V0UM5.2.3 En_MACC2 (MAC Configuration Register 2)Bits Field R/W Default Descr

CHAPTER 5 ETHERNET CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2875.2.6 En_CLRT (Collision Register)Bits Field R/W Default Description31:14

CHAPTER 5 ETHERNET CONTROLLER288Preliminary User’s Manual S15543EJ1V0UM5.2.11 En_PTVR (Pause Timer Value Read Register)Bits Field R/W Default De

CHAPTER 5 ETHERNET CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2895.2.15 En_MADR (MII Address Register)Bits Field R/W Default Description31

CHAPTER 1 INTRODUCTIONPreliminary User’s Manual S15543EJ1V0UM291.5.4 ATM cell processorBy using NEC proprietary 32-bit controller, we will realiz

CHAPTER 5 ETHERNET CONTROLLER290Preliminary User’s Manual S15543EJ1V0UM5.2.19 En_AFR (Address Filtering Register)Bits Field R/W Default Descript

CHAPTER 5 ETHERNET CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2915.2.22 En_CAR1 (Carry Register 1)The bits of this register indicate that

CHAPTER 5 ETHERNET CONTROLLER292Preliminary User’s Manual S15543EJ1V0UM5.2.23 En_CAR2 (Carry Register 2)The bits of this register indicate that

CHAPTER 5 ETHERNET CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2935.2.24 En_CAM1 (Carry Register 1 Mask Register)This register masks the In

CHAPTER 5 ETHERNET CONTROLLER294Preliminary User’s Manual S15543EJ1V0UM5.2.25 En_CAM2 (Carry Register 2 Mask Register)This register masks the In

CHAPTER 5 ETHERNET CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2955.2.27 En_TXFCR (Transmit FIFO Control Register)Bits Field R/W Default De

CHAPTER 5 ETHERNET CONTROLLER296Preliminary User’s Manual S15543EJ1V0UM5.2.28 En_TXDPR (Transmit Descriptor Pointer)Bits Field R/W Default Descr

CHAPTER 5 ETHERNET CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2975.2.30 En_RXFCR (Receive FIFO Control Register)Bits Field R/W Default Des

CHAPTER 5 ETHERNET CONTROLLER298Preliminary User’s Manual S15543EJ1V0UM5.2.32 En_RXPDR (Receive Pool Descriptor Pointer)Bits Field R/W Default D

CHAPTER 5 ETHERNET CONTROLLERPreliminary User’s Manual S15543EJ1V0UM2995.2.35 En_MSR (Mask Serves Register)Each interrupt source is maskable. En

Preliminary User’s Manual S15543EJ1V0UM3SUMMARY OF CONTENTSCHAPTER 1 INTRODUCTION ...

CHAPTER 1 INTRODUCTION30Preliminary User’s Manual S15543EJ1V0UM1.5.5 Ethernet controllerEthernet Controller supports 2-channel 10 Mbps/100 Mbps E

CHAPTER 5 ETHERNET CONTROLLER300Preliminary User’s Manual S15543EJ1V0UM5.3 Operation5.3.1 InitializationAfter a power on reset or a software re

CHAPTER 5 ETHERNET CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3015.3.3 Buffer descriptor formatThe Transmit Descriptor format is shown in

CHAPTER 5 ETHERNET CONTROLLER302Preliminary User’s Manual S15543EJ1V0UMTable 5-7. Attribute for Receive DescriptorAttribute & Size Bit Name

CHAPTER 5 ETHERNET CONTROLLERPreliminary User’s Manual S15543EJ1V0UM303Short frames are automatically padded by the transmit logic if PADEN bit i

CHAPTER 5 ETHERNET CONTROLLER304Preliminary User’s Manual S15543EJ1V0UMFigure 5-7. Transmit ProcedureVR4120A Ethernet Controller External PHY De

CHAPTER 5 ETHERNET CONTROLLERPreliminary User’s Manual S15543EJ1V0UM305Operation flow for transmit packeti) Prepares transmit data in data buffer

CHAPTER 5 ETHERNET CONTROLLER306Preliminary User’s Manual S15543EJ1V0UMWhen the receive frame is complete, Ethernet Controller sets the L-bit in

CHAPTER 5 ETHERNET CONTROLLERPreliminary User’s Manual S15543EJ1V0UM307Operation flow for receive packeti) Prepares the receive buffer descriptor

CHAPTER 5 ETHERNET CONTROLLER308Preliminary User’s Manual S15543EJ1V0UM(3) Broadcast address filteringAll of received packets with broadcast des

Preliminary User’s Manual S15543EJ1V0UM309CHAPTER 6 USB CONTROLLER6.1 OverviewThe USB Controller handles the data communication through USB. The

CHAPTER 1 INTRODUCTIONPreliminary User’s Manual S15543EJ1V0UM311.5.6 USB controllerUSB Controller provides Full Speed Function device function de

CHAPTER 6 USB CONTROLLER310Preliminary User’s Manual S15543EJ1V0UM6.1.2 Internal block diagramUSB Controller internal block diagram is as shown

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3116.2 RegistersThis section explains the mapping of those registers that can be

CHAPTER 6 USB CONTROLLER312Preliminary User’s Manual S15543EJ1V0UM2. All internal registers are 32-bit word-aligned registers.3. The burst access

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3136.2.2 U_GMR (USB General Mode Register)This register is used for setting the o

CHAPTER 6 USB CONTROLLER314Preliminary User’s Manual S15543EJ1V0UM6.2.4 U_GSR1 (USB General Status Register 1)This register indicates the curren

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM315Bits Field R/W Default Description8 EP1FU RC 0 EP1 FIFO Error:Bit that indicate

CHAPTER 6 USB CONTROLLER316Preliminary User’s Manual S15543EJ1V0UM6.2.5 U_IMR1 (USB Interrupt Mask Register 1)This register is used to mask inte

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM317Bits Field R/W Default Description4 EP3TF R/W 0 EP3 Tx Finished:1 = unmask.0 =

CHAPTER 6 USB CONTROLLER318Preliminary User’s Manual S15543EJ1V0UM6.2.6 U_GSR2 (USB General Status Register 2)This register indicates the curren

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3196.2.7 U_IMR2 (USB Interrupt Mask Register 2)This register is used to mask inte

CHAPTER 1 INTRODUCTION32Preliminary User’s Manual S15543EJ1V0UM1.5.7 PCI controllerPCI Controller provides PCI Bus function defined by PCI SIG. T

CHAPTER 6 USB CONTROLLER320Preliminary User’s Manual S15543EJ1V0UM6.2.8 U_EP0CR (USB EP0 Control Register)This register is used for setting the

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3216.2.9 U_EP1CR (USB EP1 Control Register)This register is used for setting the

CHAPTER 6 USB CONTROLLER322Preliminary User’s Manual S15543EJ1V0UM6.2.11 U_EP3CR (USB EP3 Control Register)This register is used for setting the

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3236.2.12 U_EP4CR (USB EP4 Control Register)This register is used for setting the

CHAPTER 6 USB CONTROLLER324Preliminary User’s Manual S15543EJ1V0UM6.2.13 U_EP5CR (USB EP5 Control Register)This register is used for setting the

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3256.2.15 U_CMR (USB Command Register)This register is used for issuing Tx reques

CHAPTER 6 USB CONTROLLER326Preliminary User’s Manual S15543EJ1V0UM6.2.17 U_TEPSR (USB Tx EndPoint Status Register)This register is used for indi

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3276.2.19 U_RP0AR (USB Rx Pool0 Address Register)This register indicates the star

CHAPTER 6 USB CONTROLLER328Preliminary User’s Manual S15543EJ1V0UM6.2.22 U_RP2IR (USB Rx Pool2 Information Register)This register indicates the

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3296.2.27 U_TMWA (USB Tx MailBox Write Address Register)Bits Field R/W Default De

CHAPTER 1 INTRODUCTIONPreliminary User’s Manual S15543EJ1V0UM331.6 Pin Configuration (Bottom View)• 500-pin Tape BGA (Heat spread type) (40 × 40)

CHAPTER 6 USB CONTROLLER330Preliminary User’s Manual S15543EJ1V0UM6.3 USB Attachment SequenceThis section describes the sequence that is followe

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3316.4 InitializationAfter USB Controller has been reset, the VR4120A must set se

CHAPTER 6 USB CONTROLLER332Preliminary User’s Manual S15543EJ1V0UM6.4.1 Receive pool settingsFor details of the receive pool settings, see Secti

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM333Figure 6-3. Mailbox Configuration31 0U_TMSA(U_RMSA)U_TMWA(U_RMWA)U_TMBA(U_RMBA

CHAPTER 6 USB CONTROLLER334Preliminary User’s Manual S15543EJ1V0UM6.5 Data Transmit FunctionThis section explains USB Controller's data tra

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM335Figure 6-5. Tx Buffer ConfigurationBuffer descriptorBuffer descriptorBuffer de

CHAPTER 6 USB CONTROLLER336Preliminary User’s Manual S15543EJ1V0UMFigure 6-6. Configuration of Transmit Buffer Directory-Tx Buffer DirectoryDire

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3376.5.3 Data transmit modesUSB Controller supports two transmit modes. These mod

CHAPTER 6 USB CONTROLLER338Preliminary User’s Manual S15543EJ1V0UM6.5.4 VR4120A processing at data transmittingThis section explains the process

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM339(1) First, the VR4120A prepares the data to be transmitted in system memory.(2)

CHAPTER 1 INTRODUCTION34Preliminary User’s Manual S15543EJ1V0UMPin Name(1/3)Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pi

CHAPTER 6 USB CONTROLLER340Preliminary User’s Manual S15543EJ1V0UMFigure 6-9. Transmit Status Register31 15EP301623 8EP5 EP07EP124USB Tx EndPoin

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3416.5.5 USB controller processing at data transmittingThis section presents all

CHAPTER 6 USB CONTROLLER342Preliminary User’s Manual S15543EJ1V0UMNumbers (1) to (15) do not indicate the order in which USB Controller must perf

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3436.5.6 Tx indicationFor every data segment to be transmitted, USB Controller wr

CHAPTER 6 USB CONTROLLER344Preliminary User’s Manual S15543EJ1V0UM6.6 Data Receive FunctionThis section explains USB Controller's data rece

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3456.6.2 Rx Buffer configurationData received from the USB is stored into a recei

CHAPTER 6 USB CONTROLLER346Preliminary User’s Manual S15543EJ1V0UMFigure 6-14. Receive Descriptor Configuration-Rx Buffer DirectoryBuffer Direct

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3476.6.3 Receive pool settingsUSB Controller uses three receive pools.Pool0 For E

CHAPTER 6 USB CONTROLLER348Preliminary User’s Manual S15543EJ1V0UM(a) If any unused Buffer Directories remain in the pool (when the RNOD field in

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM349(1) Reception in EndPoint0, EndPoint6Same processing is executed without relati

CHAPTER 1 INTRODUCTIONPreliminary User’s Manual S15543EJ1V0UM35(2/3)Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pi

CHAPTER 6 USB CONTROLLER350Preliminary User’s Manual S15543EJ1V0UM(3) EndPoint2, EndPoint4, assemble modeThe processing in EndPoint2, EndPoint4 r

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3516.6.5 VR4120A receive processingThis section explains the processing that the

CHAPTER 6 USB CONTROLLER352Preliminary User’s Manual S15543EJ1V0UM6.6.6 USB controller receive processingThis section presents all of the proces

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM353Numbers (1) to (9) do not indicate the order in which USB Controller must perfo

CHAPTER 6 USB CONTROLLER354Preliminary User’s Manual S15543EJ1V0UM6.6.6.2 Assemble modeThe following figure illustrates the receive operations p

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM355Numbers (1) to (11) do not indicate the order in which USB Controller must perf

CHAPTER 6 USB CONTROLLER356Preliminary User’s Manual S15543EJ1V0UM6.6.6.3 Separate modeThe following figure illustrates the receive operations p

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM357Numbers (1) to (12) do not indicate the order in which USB Controller must perf

CHAPTER 6 USB CONTROLLER358Preliminary User’s Manual S15543EJ1V0UM6.6.7 Detection of errors on USBUSB Controller has some functions which detect

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM359data to USB and will set EP1ND bit (Bit 2) in USB GeneralStatus Register 2.• Ex

CHAPTER 1 INTRODUCTION36Preliminary User’s Manual S15543EJ1V0UM(3/3)Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pi

CHAPTER 6 USB CONTROLLER360Preliminary User’s Manual S15543EJ1V0UM6.6.8 Rx data corruption on Isochronous EndPointOn Isochronous Rx EndPoint (EP

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM361Figure 6-25. Example of Buffers Including Corrupted DataBuffer descriptorBuffe

CHAPTER 6 USB CONTROLLER362Preliminary User’s Manual S15543EJ1V0UM(b) Rx assemble modeUSB Controller sets EP2FO (EndPoint2 No Data) bit (Bit 9) i

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM363When set to a ‘1’, indicates that a buffer overrun occurred.This bit is set onl

CHAPTER 6 USB CONTROLLER364Preliminary User’s Manual S15543EJ1V0UM6.7 Power ManagementUSB Controller has a built in feature that allows it to us

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM365The VR4120A is not permitted to write to other than USB Controller's USB G

CHAPTER 6 USB CONTROLLER366Preliminary User’s Manual S15543EJ1V0UM6.7.3 Remote wake upThe Remote Wake Up sequence is shown below.Figure 6-29. R

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3676.8 Receiving SOF PacketUSB Controller can receive SOF Packets, and check if F

CHAPTER 6 USB CONTROLLER368Preliminary User’s Manual S15543EJ1V0UM6.9 Loopback ModeUSB Controller features a built-in loopback function for test

CHAPTER 6 USB CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3696.10 Example of ConnectionUSB Controller is connected to the µPD98502 internal

CHAPTER 1 INTRODUCTIONPreliminary User’s Manual S15543EJ1V0UM371.7 Pin FunctionSymbol of I/O column indicates following status in this section.I

370Preliminary User’s Manual S15543EJ1V0UMCHAPTER 7 PCI CONTROLLER7.1 OverviewThe PCI Controller supports both NIC mode and Host mode. With the N

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3717.2 Bus Bridge Functions7.2.1 Internal bus to PCI transaction7.2.1.1 Window s

CHAPTER 7 PCI CONTROLLER372Preliminary User’s Manual S15543EJ1V0UM7.2.1.3 Write issue from internal bus to PCI(1) Posted write transactionIf IPW

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM373(2) Non posted write transactionIf IPWRD bit in P_BCNT register is ‘1’, the PCI

CHAPTER 7 PCI CONTROLLER374Preliminary User’s Manual S15543EJ1V0UM7.2.1.4 Read issue from internal bus to PCI(1) Delayed read transactionWhen ID

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM375(2) Non delayed read transactionWhen IDRTD bit in P_BCNT register is ‘1’, the PC

CHAPTER 7 PCI CONTROLLER376Preliminary User’s Manual S15543EJ1V0UM7.2.2 PCI to internal bus transaction7.2.2.1 Window sizeThe PCI Controller su

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3777.2.2.3 Write issue from PCI to Internal bus(1) Posted write transactionIf PPWR

CHAPTER 7 PCI CONTROLLER378Preliminary User’s Manual S15543EJ1V0UM(2) Non posted write transactionWhen PPWRD bit in P_BCNT register is ‘1’, the P

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3797.2.2.4 Read issue from PCI to internal bus(1) Delayed read transactionWhen PDR

CHAPTER 1 INTRODUCTION38Preliminary User’s Manual S15543EJ1V0UM1.7.4 System control interfacePin Name Pin No. I/O Active Level FunctionSCLK V1 I

CHAPTER 7 PCI CONTROLLER380Preliminary User’s Manual S15543EJ1V0UM(2) Non delayed read transactionWhen PDRTD bit in P_BCNT register is ‘1’, the P

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3817.2.3 Abnormal Termination7.2.3.1 On PCI bus(1) Detecting parity errorWhen the

CHAPTER 7 PCI CONTROLLER382Preliminary User’s Manual S15543EJ1V0UMIn the case that the value except for ‘0’ is set to P_RTMR register, the PCI Co

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3837.3 PCI Power Management InterfaceThe PCI Controller has the mechanism for powe

CHAPTER 7 PCI CONTROLLER384Preliminary User’s Manual S15543EJ1V0UM7.3.4 Power state transition7.3.4.1 Transition by issue from PCI-HostAn examp

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3857.3.4.2 Transition by power management eventThe sequence is as follows:1. When

CHAPTER 7 PCI CONTROLLER386Preliminary User’s Manual S15543EJ1V0UM7.4 Functions in Host-modeThe functions described in this section are availabl

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3877.4.1.3 PCI Configuration Data Register (P_PCDR)When bit31 in the PCAR register

CHAPTER 7 PCI CONTROLLER388Preliminary User’s Manual S15543EJ1V0UMFigure 7-14. An Example How to Connect AD [31:16] Signal Line to IDSEL PortAD[

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM389Figure 7-16. Arbitration in Alternating ModePCIControllerGNT#0GNT#3GNT#1GNT#2Ro

CHAPTER 1 INTRODUCTIONPreliminary User’s Manual S15543EJ1V0UM391.7.5 Memory interface(1/2)Pin Name Pin No. I/O Active Level FunctionSDCLK0 L1 O S

CHAPTER 7 PCI CONTROLLER390Preliminary User’s Manual S15543EJ1V0UM7.5 Registers7.5.1 Register mapR/WOffset Address Register NameInternalbusPCIA

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3917.5.2 P_PLBA (PCI Lower Base Address Register)When the PCI Controller issues 32

CHAPTER 7 PCI CONTROLLER392Preliminary User’s Manual S15543EJ1V0UM7.5.5 P_PCAR (PCI Configuration Address Register)PCAR register is used to set

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3937.5.7 P_IGSR (Internal Bus-side General Status Register)IGSR register shows the

CHAPTER 7 PCI CONTROLLER394Preliminary User’s Manual S15543EJ1V0UM7.5.8 P_IIMR (Internal Bus Interrupt Mask Register)IIMR register masks the int

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3957.5.9 P_PGSR (PCI-side General Status Register)PGSR register shows the interrup

CHAPTER 7 PCI CONTROLLER396Preliminary User’s Manual S15543EJ1V0UM7.5.10 P_IIMR (Internal Bus Interrupt Mask Register)IIMR register masks the in

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3977.5.11 P_PIMR (PCI Interrupt Mask Register)PIMR register masks interruptions. A

CHAPTER 7 PCI CONTROLLER398Preliminary User’s Manual S15543EJ1V0UM7.5.12 P_HMCR (Host Mode Control Register)This register is used to control the

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM3997.5.15 P_BCNT (Bridge Control Register)This register is used to control the PCI

Preliminary User’s Manual S15543EJ1V0UM4NOTES FOR CMOS DEVICES1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORSNote:Strong electric field, when exposed to

CHAPTER 1 INTRODUCTION40Preliminary User’s Manual S15543EJ1V0UM(2/2)Pin Name Pin No. I/O Active Level FunctionSMD11 R5 I/O Memory dataSMD12 R2 I/O

CHAPTER 7 PCI CONTROLLER400Preliminary User’s Manual S15543EJ1V0UM7.5.16 P_PPCR (PCI Power Control Register)This register is used to control the

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM4017.5.18 P_RTMR (Retry Timer Register)This register is used to set the limitation

CHAPTER 7 PCI CONTROLLER402Preliminary User’s Manual S15543EJ1V0UMOffset Address Register Name Size(byte)InternalbusPCI Description1000_4100H Ven

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM4037.5.19.2 Vendor ID registerThis register identifies the manufacturer of the dev

CHAPTER 7 PCI CONTROLLER404Preliminary User’s Manual S15543EJ1V0UM7.5.19.4 Command registerThis register provides coarse control over a device’s

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM4057.5.19.5 Status registerThis register is used to show PCI bus related events st

CHAPTER 7 PCI CONTROLLER406Preliminary User’s Manual S15543EJ1V0UM7.5.19.6 Revision ID registerThis register specifies a device specific revisio

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM4077.5.19.10 Header type registerThis register identifies the layout of the second

CHAPTER 7 PCI CONTROLLER408Preliminary User’s Manual S15543EJ1V0UM7.5.19.14 Subsystem ID registerThis register is used to uniquely identify the

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM4097.5.19.19 Max_Lat registerThis register specifies how often the device needs to

CHAPTER 1 INTRODUCTIONPreliminary User’s Manual S15543EJ1V0UM411.7.6 PCI interface(1/2)Pin Name Pin No. I/O Active Level FunctionPSCLK V30 I PCI

CHAPTER 7 PCI CONTROLLER410Preliminary User’s Manual S15543EJ1V0UM7.5.19.23 PMCSR registerThis register is used to manage the PCI function’s pow

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM4117.6 Information for Software7.6.1 NIC mode7.6.1.1 Initialization(1) Initializ

CHAPTER 7 PCI CONTROLLER412Preliminary User’s Manual S15543EJ1V0UM- Sets a ‘1’ to PME_En bit in PMCSR register, if neededThen, the PCI-Host devic

CHAPTER 7 PCI CONTROLLERPreliminary User’s Manual S15543EJ1V0UM413- Sets a ‘1’ to “Bus Master Enable” bit in command register, if the chip execute

414Preliminary User’s Manual S15543EJ1V0UMCHAPTER 8 UART8.1 OverviewUART is a serial interface that conforms to the RS-232C communication standar

CHAPTER 8 UARTPreliminary User’s Manual S15543EJ1V0UM4158.3 RegistersThis controller uses the NEC NA16550L Mega-Function as its internal UART. Th

CHAPTER 8 UART416Preliminary User’s Manual S15543EJ1V0UM8.3.2 UARTRBR (UART Receiver data Buffer Register)This register holds receive data. It i

CHAPTER 8 UARTPreliminary User’s Manual S15543EJ1V0UM4178.3.6 UARTDLM (UART Divisor Latch MSB Register)This register is used to set the divisor (

CHAPTER 8 UART418Preliminary User’s Manual S15543EJ1V0UM8.3.7 UARTIIR (UART Interrupt ID Register)This register indicates priority levels for in

CHAPTER 8 UARTPreliminary User’s Manual S15543EJ1V0UM4198.3.8 UARTFCR (UART FIFO Control Register)This register is used to control the FIFOs: ena

CHAPTER 1 INTRODUCTION42Preliminary User’s Manual S15543EJ1V0UM(2/2)Pin Name Pin No. I/O Active Level FunctionPAD11 J28 I/OZ PCI address and dataP

CHAPTER 8 UART420Preliminary User’s Manual S15543EJ1V0UM8.3.9 UARTLCR (UART Line Control Register)This register is used to specify the format fo

CHAPTER 8 UARTPreliminary User’s Manual S15543EJ1V0UM4218.3.10 UARTMCR (UART Modem Control Register)This register controls the state of external

CHAPTER 8 UART422Preliminary User’s Manual S15543EJ1V0UM8.3.11 UARTLSR (UART Line Status Register)This register reports the current state of the

CHAPTER 8 UARTPreliminary User’s Manual S15543EJ1V0UM4238.3.12 UARTMSR (UART Modem Status Register)This register reports the current state of and

424Preliminary User’s Manual S15543EJ1V0UMCHAPTER 9 TIMER9.1 OverviewThere are two Timers. The timers are clocked at the system clock rate. All t

CHAPTER 9 TIMERPreliminary User’s Manual S15543EJ1V0UM4259.3 Registers9.3.1 Register mapOffset Address Register Name R/W Access Description1000_

CHAPTER 9 TIMER426Preliminary User’s Manual S15543EJ1V0UM9.3.3 TM0CSR (Timer CH0 Count Set Register)The Timer CH0 Count Set Register “TM0CSR” is

Preliminary User’s Manual S15543EJ1V0UM427CHAPTER 10 MICRO WIRE10.1 OverviewThis EEPROM interface is compatible with the Micro Wire serial inter

CHAPTER 10 MICRO WIRE428Preliminary User’s Manual S15543EJ1V0UM10.2 Operations10.2.1 Data read at the power up loadAfter reset release, power

CHAPTER 10 MICRO WIREPreliminary User’s Manual S15543EJ1V0UM42910.3 Registers10.3.1 Register mapOffset Address Register Name R/W Access Descrip

CHAPTER 1 INTRODUCTIONPreliminary User’s Manual S15543EJ1V0UM431.7.7 ATM interface1.7.7.1 UTOPIA management interfacePin Name Pin No. I/O Active

CHAPTER 10 MICRO WIRE430Preliminary User’s Manual S15543EJ1V0UM10.3.6 MACAR3 (MAC Address Register 3)Bits Field R/W Default Description31:16 SE

Preliminary User’s Manual S15543EJ1V0UM431APPENDIX A MIPS III INSTRUCTION SET DETAILSThis chapter provides a detailed description of the opera

APPENDIX A MIPS III INSTRUCTION SET DETAILS432Preliminary User’s Manual S15543EJ1V0UMTable A-1. CPU Instruction Operation NotationsSymbol Des

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM433(1) Instruction notation examplesThe following examples

APPENDIX A MIPS III INSTRUCTION SET DETAILS434Preliminary User’s Manual S15543EJ1V0UMAs shown in Table A-3, the Access Type field indicates th

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM435A.4 System Control Coprocessor (CP0) InstructionsTh

APPENDIX A MIPS III INSTRUCTION SET DETAILS436Preliminary User’s Manual S15543EJ1V0UMADDAddADDrsSPECIAL0 0 0 0 0 0rt rd00 0 0 0 0ADD1 0 0 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM437ADDIAdd ImmediateADDIrsADDI0 0 1 0 0 0rt immediate31 26

APPENDIX A MIPS III INSTRUCTION SET DETAILS438Preliminary User’s Manual S15543EJ1V0UMADDIUAdd Immediate UnsignedADDIUrsADDIU0 0 1 0 0 1rt imme

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM439ADDUAdd UnsignedADDUrsSPECIAL0 0 0 0 0 0rt rd00 0 0 0 0A

CHAPTER 1 INTRODUCTION44Preliminary User’s Manual S15543EJ1V0UM1.7.7.2 UTOPIA data interfacePin Name Pin No. I/O Active Level FunctionCLKUSL0 T4

APPENDIX A MIPS III INSTRUCTION SET DETAILS440Preliminary User’s Manual S15543EJ1V0UMANDAndANDrsSPECIAL0 0 0 0 0 0rt rd00 0 0 0 0AND1 0 0 1 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM441ANDIAnd ImmediateANDIrsANDI0 0 1 1 0 0rt immediate31 26

APPENDIX A MIPS III INSTRUCTION SET DETAILS442Preliminary User’s Manual S15543EJ1V0UMBC0FBranch On Coprocessor 0 FalseBC0FBC0 1 0 0 0COPz0 1 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM443BC0FLBranch On Coprocessor 0 False Likely (1/2)BC0FLBC0

APPENDIX A MIPS III INSTRUCTION SET DETAILS444Preliminary User’s Manual S15543EJ1V0UMBC0FLBranch On Coprocessor 0 False Likely (2/2)BC0FLOpcod

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM445BC0TBranch On Coprocessor 0 TrueBC0TBC0 1 0 0 0COPz0 1 0

APPENDIX A MIPS III INSTRUCTION SET DETAILS446Preliminary User’s Manual S15543EJ1V0UMBC0TLBranch On Coprocessor 0 True Likely (1/2)BC0TLBC0 1

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM447BC0TLBranch On Coprocessor 0 True Likely (2/2)BC0TLOpcod

APPENDIX A MIPS III INSTRUCTION SET DETAILS448Preliminary User’s Manual S15543EJ1V0UMBEQBranch On EqualBEQrsBEQ0 0 0 1 0 0rt offset31 26 25 21

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM449BEQLBranch On Equal LikelyBEQLrsBEQL0 1 0 1 0 0rt offset

CHAPTER 1 INTRODUCTIONPreliminary User’s Manual S15543EJ1V0UM451.7.8 Ethernet interface1.7.8.1 Ethernet interface (Channel 1)Pin Name Pin No. I/

APPENDIX A MIPS III INSTRUCTION SET DETAILS450Preliminary User’s Manual S15543EJ1V0UMBGEZBranch On Greater Than Or Equal To ZeroBGEZrsREGIMM0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM451BGEZALBranch On Greater Than Or Equal To Zero And LinkBG

APPENDIX A MIPS III INSTRUCTION SET DETAILS452Preliminary User’s Manual S15543EJ1V0UMBGEZALLBranch On Greater Than Or Equal To Zero And Link L

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM453BGEZLBranch On Greater Than Or Equal To Zero LikelyBGEZL

APPENDIX A MIPS III INSTRUCTION SET DETAILS454Preliminary User’s Manual S15543EJ1V0UMBGTZBranch On Greater Than ZeroBGTZrsBGTZ0 0 0 1 1 100 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM455BGTZLBranch On Greater Than Zero LikelyBGTZLrsBGTZL0 1 0

APPENDIX A MIPS III INSTRUCTION SET DETAILS456Preliminary User’s Manual S15543EJ1V0UMBLEZBranch On Less Than Or Equal To ZeroBLEZrsBLEZ0 0 0 1

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM457BLEZLBranch On Less Than Or Equal To Zero LikelyBLEZLrsB

APPENDIX A MIPS III INSTRUCTION SET DETAILS458Preliminary User’s Manual S15543EJ1V0UMBLTZBranch On Less Than ZeroBLTZrsREGIMM0 0 0 0 0 1BLTZ0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM459BLTZALBranch On Less Than Zero And LinkBLTZALrsREGIMM0 0

CHAPTER 1 INTRODUCTION46Preliminary User’s Manual S15543EJ1V0UM1.7.8.2 Ethernet interface (Channel 2)Pin Name Pin No. I/O Active Level FunctionMI

APPENDIX A MIPS III INSTRUCTION SET DETAILS460Preliminary User’s Manual S15543EJ1V0UMBLTZALLBranch On Less Than Zero And Link LikelyBLTZALLrsR

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM461BLTZLBranch On Less Than Zero LikelyBLTZLrsREGIMM0 0 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILS462Preliminary User’s Manual S15543EJ1V0UMBNEBranch On Not EqualBNErsBNE0 0 0 1 0 1rt offset31 26 2

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM463BNELBranch On Not Equal LikelyBNELrsBNEL0 1 0 1 0 1rt of

APPENDIX A MIPS III INSTRUCTION SET DETAILS464Preliminary User’s Manual S15543EJ1V0UMBREAKBreakpointBREAKcodeSPECIAL0 0 0 0 0 0BREAK0 0 1 1 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM465CACHECache (1/4)CACHEbaseCACHE1 0 1 1 1 1op offset31 26

APPENDIX A MIPS III INSTRUCTION SET DETAILS466Preliminary User’s Manual S15543EJ1V0UMCACHECache (2/4)CACHEWrite back from a cache goes to main

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM467CACHECache (3/4)CACHECode Cache Name Operation0 I Index_

APPENDIX A MIPS III INSTRUCTION SET DETAILS468Preliminary User’s Manual S15543EJ1V0UMCACHECache (4/4)CACHEOperation:32, 64 T:vAddr ← ((offset

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM469DADDDoubleword AddDADDrsSPECIAL0 0 0 0 0 0rt rd00 0 0 0

CHAPTER 1 INTRODUCTIONPreliminary User’s Manual S15543EJ1V0UM471.7.10 UART interfacePin Name Pin No. I/O Active Level FunctionURCLK D9 I UART ext

APPENDIX A MIPS III INSTRUCTION SET DETAILS470Preliminary User’s Manual S15543EJ1V0UMDADDIDoubleword Add ImmediateDADDIrsDADDI0 1 1 0 0 0rt im

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM471DADDIUDoubleword Add Immediate UnsignedDADDIUrsDADDIU0 1

APPENDIX A MIPS III INSTRUCTION SET DETAILS472Preliminary User’s Manual S15543EJ1V0UMDADDUDoubleword Add UnsignedDADDUrsSPECIAL0 0 0 0 0 0rt r

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM473DDIVDoubleword DivideDDIVrsSPECIAL0 0 0 0 0 0rt00 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILS474Preliminary User’s Manual S15543EJ1V0UMDDIVUDoubleword Divide UnsignedDDIVUrsSPECIAL0 0 0 0 0 0r

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM475DIVDivideDIVrsSPECIAL0 0 0 0 0 0rt00 0 0 0 0 0 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILS476Preliminary User’s Manual S15543EJ1V0UMDIVUDivide UnsignedDIVUrsSPECIAL0 0 0 0 0 0rt00 0 0 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM477DMACCDoubleword Multiply and Accumulate (1/3)DMACCrsSPEC

APPENDIX A MIPS III INSTRUCTION SET DETAILS478Preliminary User’s Manual S15543EJ1V0UMDMACCDoubleword Multiply and Accumulate (2/3)DMACC• When

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM479DMACCDoubleword Multiply and Accumulate (3/3)DMACCOperat

CHAPTER 1 INTRODUCTION48Preliminary User’s Manual S15543EJ1V0UM1.7.14 I.C. – openPin Name Pin No. I/O Active Level FunctionIC-OPEN A17, A19, A20,

APPENDIX A MIPS III INSTRUCTION SET DETAILS480Preliminary User’s Manual S15543EJ1V0UMDMFC0 Doubleword Move From System Control Coprocessor DMF

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM481DMTC0Doubleword Move To System Control CoprocessorDMTC0D

APPENDIX A MIPS III INSTRUCTION SET DETAILS482Preliminary User’s Manual S15543EJ1V0UMDMULTDoubleword MultiplyDMULTrsSPECIAL0 0 0 0 0 0rt00 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM483DMULTUDoubleword Multiply UnsignedDMULTUrsSPECIAL0 0 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILS484Preliminary User’s Manual S15543EJ1V0UMDSLLDoubleword Shift Left LogicalDSLL00 0 0 0 0SPECIAL0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM485DSLLVDoubleword Shift Left Logical VariableDSLLVrsSPECIA

APPENDIX A MIPS III INSTRUCTION SET DETAILS486Preliminary User’s Manual S15543EJ1V0UMDSLL32Doubleword Shift Left Logical + 32DSLL3200 0 0 0 0S

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM487DSRADoubleword Shift Right ArithmeticDSRA00 0 0 0 0SPECI

APPENDIX A MIPS III INSTRUCTION SET DETAILS488Preliminary User’s Manual S15543EJ1V0UMDSRAVDoubleword Shift Right Arithmetic VariableDSRAVrsSPE

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM489DSRA32Doubleword Shift Right Arithmetic + 32DSRA3200 0 0

CHAPTER 1 INTRODUCTIONPreliminary User’s Manual S15543EJ1V0UM491.8 I/O Register MapCore Offset RegisterLength(Byte)Name Access byVR4120ADescripti

APPENDIX A MIPS III INSTRUCTION SET DETAILS490Preliminary User’s Manual S15543EJ1V0UMDSRLDoubleword Shift Right LogicalDSRL00 0 0 0 0SPECIAL0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM491DSRLVDoubleword Shift Right Logical VariableDSRLVrsSPECI

APPENDIX A MIPS III INSTRUCTION SET DETAILS492Preliminary User’s Manual S15543EJ1V0UMDSRL32Doubleword Shift Right Logical + 32DSRL3200 0 0 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM493DSUBDoubleword SubtractDSUBrsSPECIAL0 0 0 0 0 0rt rd00 0

APPENDIX A MIPS III INSTRUCTION SET DETAILS494Preliminary User’s Manual S15543EJ1V0UMDSUBUDoubleword Subtract UnsignedDSUBUrsSPECIAL0 0 0 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM495ERETException ReturnERETCO1COP00 1 0 0 0 000 0 0 0 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILS496Preliminary User’s Manual S15543EJ1V0UMHIBERNATEHibernateHIBERNATECO1COP00 1 0 0 0 000 0 0 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM497JJumpJJ0 0 0 0 1 0target31 26 25 0626Format:J targetDesc

APPENDIX A MIPS III INSTRUCTION SET DETAILS498Preliminary User’s Manual S15543EJ1V0UMJALJump And LinkJALJAL0 0 0 0 1 1target31 26 25 0626Forma

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM499JALRJump And Link RegisterJALRrsSPECIAL0 0 0 0 0 000 0 0

Preliminary User’s Manual S15543EJ1V0UM5VR4100, VR4102, VR4111, VR4120A, VR4300, VR4305, VR4310, VR4400, VR5000, VR10000, VR Series, VR4000Series, VR

CHAPTER 1 INTRODUCTION50Preliminary User’s Manual S15543EJ1V0UMCore Offset RegisterLength(Byte)Name Access byVR4120ADescriptionPCI 048H-04CH 4 N/A

APPENDIX A MIPS III INSTRUCTION SET DETAILS500Preliminary User’s Manual S15543EJ1V0UMJALXJump And Link ExchangeJALXJALX01110131 26 25 0626targ

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM501JRJump RegisterJRrsSPECIAL0 0 0 0 0 000 0 0 0 0 0 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILS502Preliminary User’s Manual S15543EJ1V0UMLBLoad ByteLBbaseLB1 0 0 0 0 0rt offset31 26 25 21 20 16

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM503LBULoad Byte UnsignedLBUbaseLBU1 0 0 1 0 0rt offset31 26

APPENDIX A MIPS III INSTRUCTION SET DETAILS504Preliminary User’s Manual S15543EJ1V0UMLDLoad DoublewordLDbaseLD1 1 0 1 1 1rt offset31 26 25 21

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM505LDLLoad Doubleword Left (1/3)LDLbaseLDL0 1 1 0 1 0rt off

APPENDIX A MIPS III INSTRUCTION SET DETAILS506Preliminary User’s Manual S15543EJ1V0UMLDLLoad Doubleword Left (2/3)LDLThe contents of general r

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM507LDLLoad Doubleword Left (3/3)LDLGiven a doubleword in a

APPENDIX A MIPS III INSTRUCTION SET DETAILS508Preliminary User’s Manual S15543EJ1V0UMLDRLoad Doubleword Right (1/3)LDRbaseLDR0 1 1 0 1 1rt off

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM509LDRLoad Doubleword Right (2/3)LDRThe contents of general

CHAPTER 1 INTRODUCTIONPreliminary User’s Manual S15543EJ1V0UM51Core Offset RegisterLength(Byte)Name Access byVR4120ADescriptionEther 1D0H 4 En_TBC

APPENDIX A MIPS III INSTRUCTION SET DETAILS510Preliminary User’s Manual S15543EJ1V0UMLDRLoad Doubleword Right (3/3)LDRGiven a doubleword in a

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM511LHLoad HalfwordLHbaseLH1 0 0 0 0 1rt offset31 26 25 21 2

APPENDIX A MIPS III INSTRUCTION SET DETAILS512Preliminary User’s Manual S15543EJ1V0UMLHULoad Halfword UnsignedLHUbaseLHU1 0 0 1 0 1rt offset31

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM513LUILoad Upper ImmediateLUI00 0 0 0 0LUI0 0 1 1 1 1rt imm

APPENDIX A MIPS III INSTRUCTION SET DETAILS514Preliminary User’s Manual S15543EJ1V0UMLWLoad WordLWbaseLW1 0 0 0 1 1rt offset31 26 25 21 20 16

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM515LWLLoad Word Left (1/3)LWLbaseLWL1 0 0 0 1 0rt offset31

APPENDIX A MIPS III INSTRUCTION SET DETAILS516Preliminary User’s Manual S15543EJ1V0UMLWLLoad Word Left (2/3)LWLThe contents of general registe

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM517LWLLoad Word Left (3/3)LWLGiven a doubleword in a regist

APPENDIX A MIPS III INSTRUCTION SET DETAILS518Preliminary User’s Manual S15543EJ1V0UMLWRLoad Word Right (1/3)LWRbaseLWR1 0 0 1 1 0rt offset31

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM519LWRLoad Word Right (2/3)LWRThe contents of general regis

CHAPTER 1 INTRODUCTION52Preliminary User’s Manual S15543EJ1V0UMCore Offset RegisterLength(Byte)Name Access byVR4120ADescriptionSYSCNT D8H 4 MACAR1

APPENDIX A MIPS III INSTRUCTION SET DETAILS520Preliminary User’s Manual S15543EJ1V0UMLWRLoad Word Right (3/3)LWRGiven a word in a register and

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM521LWULoad Word UnsignedLWUbaseLWU1 0 1 1 1 1rt offset31 26

APPENDIX A MIPS III INSTRUCTION SET DETAILS522Preliminary User’s Manual S15543EJ1V0UMMACCMultiply and Accumulate (1/5)MACCrsSPECIAL0 0 0 0 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM523MACCMultiply and Accumulate (2/5)MACC• When saturation p

APPENDIX A MIPS III INSTRUCTION SET DETAILS524Preliminary User’s Manual S15543EJ1V0UMMACCMultiply and Accumulate (3/5)MACCOperation:32, sat=0,

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM525MACCMultiply and Accumulate (4/5)MACC32, sat=1, hi=1, us

APPENDIX A MIPS III INSTRUCTION SET DETAILS526Preliminary User’s Manual S15543EJ1V0UMMACCMultiply and Accumulate (5/5)MACC64, sat=1, hi=0, us=

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM527MFC0Move From System Control CoprocessorMFC0MF0 0 0 0 0C

APPENDIX A MIPS III INSTRUCTION SET DETAILS528Preliminary User’s Manual S15543EJ1V0UMMFHIMove From HIMFHI00 0 0 0 0 0 0 0 0 0SPECIAL0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM529MFLOMove From LOMFLO00 0 0 0 0 0 0 0 0 0SPECIAL0 0

CHAPTER 1 INTRODUCTIONPreliminary User’s Manual S15543EJ1V0UM531.9 Memory MapUsing a 32-bit address, the processor physical address space encompa

APPENDIX A MIPS III INSTRUCTION SET DETAILS530Preliminary User’s Manual S15543EJ1V0UMMTC0Move To Coprocessor0MTC000 0 0 0 0 0 0 0 0 0 0COP00

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM531MTHIMove To HIrsSPECIAL0 0 0 0 0 0MTHI0 1 0 0 0 100 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILS532Preliminary User’s Manual S15543EJ1V0UMMTLOMove To LOMTLOrsSPECIAL0 0 0 0 0 0MTLO0 1 0 0 1 100 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM533MULTMultiplyMULTrsSPECIAL0 0 0 0 0 0MULT0 1 1 0 0 000 0

APPENDIX A MIPS III INSTRUCTION SET DETAILS534Preliminary User’s Manual S15543EJ1V0UMMULTUMultiply UnsignedMULTUrsSPECIAL0 0 0 0 0 0MULTU0 1 1

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM535NORNorNORrsSPECIAL0 0 0 0 0 0rt rd00 0 0 0 0NOR1 0 0 1 1

APPENDIX A MIPS III INSTRUCTION SET DETAILS536Preliminary User’s Manual S15543EJ1V0UMOROrORrsSPECIAL000000rt rd000000OR1 0 0 1 0 131 26 25 21

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM537ORIOr ImmediateORIrsORI0 0 1 1 0 1rt immediate31 26 25 2

APPENDIX A MIPS III INSTRUCTION SET DETAILS538Preliminary User’s Manual S15543EJ1V0UMSBStore ByteSBbaseSB1 0 1 0 0 0rt offset31 26 25 21 20 16

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM539SDStore DoublewordSDbaseSD1 1 1 1 1 1rt offset31 26 25 2

CHAPTER 1 INTRODUCTION54Preliminary User’s Manual S15543EJ1V0UM1.10 Reset ConfigurationThe falling edge of Clock Control Unit (CCU)’s reset line

APPENDIX A MIPS III INSTRUCTION SET DETAILS540Preliminary User’s Manual S15543EJ1V0UMSDLStore Doubleword Left (1/3)SDLbaseSDL1 0 1 1 0 0rt off

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM541SDLStore Doubleword Left (2/3)SDLAn address error except

APPENDIX A MIPS III INSTRUCTION SET DETAILS542Preliminary User’s Manual S15543EJ1V0UMSDLStore Doubleword Left (3/3)SDLGiven a doubleword in a

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM543SDRStore Doubleword Right (1/3)SDRbaseSDR1 0 1 1 0 1rt o

APPENDIX A MIPS III INSTRUCTION SET DETAILS544Preliminary User’s Manual S15543EJ1V0UMSDRStore Doubleword Right (2/3)SDRAn address error except

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM545SDRStore Doubleword Right (3/3)SDRGiven a doubleword in

APPENDIX A MIPS III INSTRUCTION SET DETAILS546Preliminary User’s Manual S15543EJ1V0UMSHStore HalfwordSHbaseSH1 0 1 0 0 1rt offset31 26 25 21 2

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM547SLLShift Left LogicalSLLSPECIAL0 0 0 0 0 0rt rd saSLL0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILS548Preliminary User’s Manual S15543EJ1V0UMSLLVShift Left Logical VariableSLLVSPECIAL0 0 0 0 0 0rt r

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM549SLTSet On Less ThanSLTrsSPECIAL0 0 0 0 0 0rt rd00 0 0 0

CHAPTER 1 INTRODUCTIONPreliminary User’s Manual S15543EJ1V0UM551.11 InterruptsThe controller supports maskable interrupts and Non-Maskable to the

APPENDIX A MIPS III INSTRUCTION SET DETAILS550Preliminary User’s Manual S15543EJ1V0UMSLTISet On Less Than ImmediateSLTIrsSLTI0 0 1 0 1 0rt imm

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM551SLTIUSet On Less Than Immediate UnsignedSLTIUrsSLTIU0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILS552Preliminary User’s Manual S15543EJ1V0UMSLTUSet On Less Than UnsignedSLTUrsSPECIAL0 0 0 0 0 0rt r

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM553SRAShift Right ArithmeticSRA00 0 0 0 0SPECIAL0 0 0 0 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILS554Preliminary User’s Manual S15543EJ1V0UMSRAVShift Right Arithmetic VariableSRAVrsSPECIAL0 0 0 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM555SRLShift Right LogicalSRL00 0 0 0 0SPECIAL0 0 0 0 0 0rt

APPENDIX A MIPS III INSTRUCTION SET DETAILS556Preliminary User’s Manual S15543EJ1V0UMSRLVShift Right Logical VariableSRLVrsSPECIAL0 0 0 0 0 0r

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM557STANDBYStandbySTANDBY000 0 0 000 0000 0000 0000COP00 1

APPENDIX A MIPS III INSTRUCTION SET DETAILS558Preliminary User’s Manual S15543EJ1V0UMSUBSubtractSUBrsSPECIAL0 0 0 0 0 0rt rd00 0 0 0 0SUB1 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM559SUBUSubtract UnsignedSUBUrsSPECIAL0 0 0 0 0 0rt rd00 0 0

CHAPTER 1 INTRODUCTION56Preliminary User’s Manual S15543EJ1V0UM1.12 Clock Control UnitThis section describe µPD98502’s internal clock is supplied

APPENDIX A MIPS III INSTRUCTION SET DETAILS560Preliminary User’s Manual S15543EJ1V0UMSUSPENDSuspendSUSPEND00 0 0 0 0 0 0 0 0 0 0 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM561SWStore WordSWbaseSW1 0 1 0 1 1rt offset31 26 25 21 20 1

APPENDIX A MIPS III INSTRUCTION SET DETAILS562Preliminary User’s Manual S15543EJ1V0UMSWLStore Word Left (1/3)SWLbaseSWL1 0 1 0 1 0rt offset31

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM563SWLStore Word Left (2/3)SWLOperation:32 T:vAddr ← ((offs

APPENDIX A MIPS III INSTRUCTION SET DETAILS564Preliminary User’s Manual S15543EJ1V0UMSWLStore Word Left (3/3)SWLGiven a doubleword in a regist

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM565SWRStore Word Right (1/3)SWRbaseSWR1 0 1 1 1 0rt offset3

APPENDIX A MIPS III INSTRUCTION SET DETAILS566Preliminary User’s Manual S15543EJ1V0UMSWRStore Word Right (2/3)SWROperation:32 T:vAddr← ((offse

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM567SWRStore Word Right (3/3)SWRGiven a doubleword in a regi

APPENDIX A MIPS III INSTRUCTION SET DETAILS568Preliminary User’s Manual S15543EJ1V0UMSYNCSynchronizeSYNCSPECIAL0 0 0 0 0 000 0 0 0 0 0 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM569SYSCALLSystem CallSYSCALLSPECIAL0 0 0 0 0 0Code31 26 25

Preliminary User’s Manual S15543EJ1V0UM57CHAPTER 2 VR4120ACaution The µµµµPD98502 doesn’t support MIPS16 instructions.This chapter describes an VR

APPENDIX A MIPS III INSTRUCTION SET DETAILS570Preliminary User’s Manual S15543EJ1V0UMTEQTrap If EqualTEQrsSPECIAL0 0 0 0 0 0rt code31 26 25 21

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM571TEQITrap If Equal ImmediateTEQIrsREGIMM0 0 0 0 0 1TEQI0

APPENDIX A MIPS III INSTRUCTION SET DETAILS572Preliminary User’s Manual S15543EJ1V0UMTGETrap If Greater Than Or EqualTGErsSPECIAL0 0 0 0 0 0rt

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM573TGEITrap If Greater Than Or Equal ImmediateTGEIrsREGIMM0

APPENDIX A MIPS III INSTRUCTION SET DETAILS574Preliminary User’s Manual S15543EJ1V0UMTGEIUTrap If Greater Than Or Equal Immediate UnsignedTGEI

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM575TGEUTrap If Greater Than Or Equal UnsignedTGEUrsSPECIAL0

APPENDIX A MIPS III INSTRUCTION SET DETAILS576Preliminary User’s Manual S15543EJ1V0UMTLBPProbe TLB For Matching EntryTLBP00 0 0 0 0 0 0 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM577TLBRRead Indexed TLB EntryTLBR00 0 0 0 0 0 0 0 0 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILS578Preliminary User’s Manual S15543EJ1V0UMTLBWIWrite Indexed TLB EntryTLBWI00 0 0 0 0 0 0 0 0 0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM579TLBWRWrite Random TLB EntryTLBWR00 0 0 0 0 0 0 0 0 0 0

CHAPTER 2 VR4120A58Preliminary User’s Manual S15543EJ1V0UM2.1.1 Internal block configuration2.1.1.1 CPUCPU has hardware resources to process an

APPENDIX A MIPS III INSTRUCTION SET DETAILS580Preliminary User’s Manual S15543EJ1V0UMTLTTrap If Less ThanTLTrsSPECIAL0 0 0 0 0 0rt code31 26 2

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM581TLTITrap If Less Than ImmediateTLTIrsREGIMM0 0 0 0 0 1TL

APPENDIX A MIPS III INSTRUCTION SET DETAILS582Preliminary User’s Manual S15543EJ1V0UMTLTIUTrap If Less Than Immediate UnsignedTLTIUrsREGIMM0 0

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM583TLTUTrap If Less Than UnsignedTLTUrsSPECIAL0 0 0 0 0 0rt

APPENDIX A MIPS III INSTRUCTION SET DETAILS584Preliminary User’s Manual S15543EJ1V0UMTNETrap If Not EqualTNErsSPECIAL0 0 0 0 0 0rt code31 26 2

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM585TNEITrap If Not Equal ImmediateTNEIrsREGIMM0 0 0 0 0 1TN

APPENDIX A MIPS III INSTRUCTION SET DETAILS586Preliminary User’s Manual S15543EJ1V0UMXORExclusive OrXORrsSPECIAL0 0 0 0 0 0rt rd00 0 0 0 0XOR1

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM587XORIExclusive OR ImmediateXORIrsXORI0 0 1 1 1 0rt immedi

APPENDIX A MIPS III INSTRUCTION SET DETAILS588Preliminary User’s Manual S15543EJ1V0UMA.6 CPU Instruction Opcode Bit EncodingFigure A-1 li

APPENDIX A MIPS III INSTRUCTION SET DETAILSPreliminary User’s Manual S15543EJ1V0UM589Figure A-1. VR4120AOpcode Bit Encoding (2/2)23...21COP0

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM592.1.2 VR4120A registersThe VR4120A has the following registers. general-purpose regist

590Preliminary User’s Manual S15543EJ1V0UMAPPENDIX B VR4120A COPROCESSOR 0 HAZARDSThe VR4120A core avoids contention of its internal resources

APPENDIX B VR4120A COPROCESSOR 0 HAZARDSPreliminary User’s Manual S15543EJ1V0UM591Table B-1. VR4120A CPU Coprocessor 0 HazardsOperation Source

APPENDIX B VR4120A COPROCESSOR 0 HAZARDS592Preliminary User’s Manual S15543EJ1V0UMRemarks 1. The instruction following MTC0 must not be MFC0.2.

APPENDIX B VR4120A COPROCESSOR 0 HAZARDSPreliminary User’s Manual S15543EJ1V0UM593(10) Instruction FetchSource: The confirmation of the operati

APPENDIX B VR4120A COPROCESSOR 0 HAZARDS594Preliminary User’s Manual S15543EJ1V0UMTable B-2 indicates examples of calculation.Table B-2. Calcu

Although NEC has taken all possible stepsto ensure that the documentation suppliedto our customers is complete, bug freeand up-to-date, we readily acc

6Preliminary User’s Manual S15543EJ1V0UMPREFACEReaders This manual is intended for engineers who need to be familiar with the capability ofthe µPD985

CHAPTER 2 VR4120A60Preliminary User’s Manual S15543EJ1V0UM2.1.3 VR4120A instruction set overviewFor CPU instructions, there are only one type of

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM612.1.4 Data formats and addressingThe VR4120A uses following four data formats:✧ Doublew

CHAPTER 2 VR4120A62Preliminary User’s Manual S15543EJ1V0UMThe following special instructions to load and store data that are not aligned on 4-byte

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM632.1.5 Coprocessors (CP0)MIPS ISA defines 4 types of coprocessors (CP0 to CP3).• CP0 tra

CHAPTER 2 VR4120A64Preliminary User’s Manual S15543EJ1V0UMTable 2-1. System Control Coprocessor (CP0) Register DefinitionsRegisterNumberRegister

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM652.1.7 CPU core memory management system (MMU)The VR4120A has a 32-bit physical addressi

CHAPTER 2 VR4120A66Preliminary User’s Manual S15543EJ1V0UM2.1.11 Instruction pipelineThe VR4120A has a 6-stage instruction pipeline. Under norma

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM672.2.2 Instruction classesThe CPU instructions are classified into five classes.2.2.2.1

CHAPTER 2 VR4120A68Preliminary User’s Manual S15543EJ1V0UMTable 2-3. Byte Specification Related to Load and Store InstructionsAccessed ByteLow-Or

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM69Table 2-4. Load/Store InstructionInstruction Format and DescriptionLoad Byte LB rt, of

Preliminary User’s Manual S15543EJ1V0UM7CONTENTSCHAPTER 1 INTRODUCTION ...

CHAPTER 2 VR4120A70Preliminary User’s Manual S15543EJ1V0UMTable 2-5. Load/Store Instruction (Extended ISA)Instruction Format and DescriptionStore

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM712.2.2.2 Computational instructionsComputational instructions perform arithmetic, logica

CHAPTER 2 VR4120A72Preliminary User’s Manual S15543EJ1V0UMTable 2-7. ALU Immediate Instruction (Extended ISA)Instruction Format and DescriptionDo

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM73Table 2-9. Three-Operand Type Instruction (Extended ISA)Instruction Format and Descript

CHAPTER 2 VR4120A74Preliminary User’s Manual S15543EJ1V0UMTable 2-11. Shift Instruction (Extended ISA)Instruction Format and DescriptionDoublewor

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM75Table 2-12. Multiply/Divide InstructionsInstruction Format and DescriptionMultiply MULT

CHAPTER 2 VR4120A76Preliminary User’s Manual S15543EJ1V0UMTable 2-13. Multiply/Divide Instructions (Extended ISA)Instruction Format and Descripti

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM77Table 2-14. Number of Stall Cycles in Multiply and Divide InstructionsInstruction Numbe

CHAPTER 2 VR4120A78Preliminary User’s Manual S15543EJ1V0UMTable 2-16. Jump InstructionInstruction Format and DescriptionJump JAL targetThe conte

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM79There are special symbols used in the instruction formats of Tables 2-17 through 2-21.RE

8Preliminary User’s Manual S15543EJ1V0UM2.1.6 Floating-point unit (FPU)...

CHAPTER 2 VR4120A80Preliminary User’s Manual S15543EJ1V0UMTable 2-18. Branch Instructions (Extended ISA)Instruction Format and DescriptionBranch

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM812.2.2.4 Special instructionsSpecial instructions generate software exceptions. Their f

CHAPTER 2 VR4120A82Preliminary User’s Manual S15543EJ1V0UMTable 2-20. Special Instructions (Extended ISA) (2/2)Instruction Format and Description

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM83Table 2-21. System Control Coprocessor (CP0) Instructions (2/2)Instruction Format and D

CHAPTER 2 VR4120A84Preliminary User’s Manual S15543EJ1V0UM2.3 PipelineThis section describes the basic operation of the VR4120A Core pipeline, wh

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM85Figure 2-10. Instruction Execution in the Pipeline(Five stages)Current CPU cyclePCycleI

CHAPTER 2 VR4120A86Preliminary User’s Manual S15543EJ1V0UMTable 2-22. Operation in Each Stage of Pipeline (MIPS III)Cycle Phase Mnemonic Descript

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM872.3.2 Branch delayDuring a VR4120A's pipeline operation, a one-cycle branch delay

CHAPTER 2 VR4120A88Preliminary User’s Manual S15543EJ1V0UM2.3.4 Pipeline operationThe operation of the pipeline is illustrated by the following e

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM892.3.4.2 Jump and link register instruction (JALR rd, rs)IF stage Same as the IF stage f

Preliminary User’s Manual S15543EJ1V0UM9CHAPTER 3 SYSTEM CONTROLLER...

CHAPTER 2 VR4120A90Preliminary User’s Manual S15543EJ1V0UM2.3.4.3 Branch on equal instruction (BEQ rs, rt, offset)IF stage Same as the IF stage f

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM912.3.4.4 Trap if less than instruction (TLT rs, rt)IF stage Same as the IF stage for the

CHAPTER 2 VR4120A92Preliminary User’s Manual S15543EJ1V0UM2.3.4.5 Load word instruction (LW rt, offset (base))IF stage Same as the IF stage for t

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM932.3.4.6 Store word instruction (SW rt, offset (base))IF stage Same as the IF stage for

CHAPTER 2 VR4120A94Preliminary User’s Manual S15543EJ1V0UM2.3.5 Interlock and exception handlingSmooth pipeline flow is interrupted when cache mi

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM95Table 2-24. Pipeline InterlockInterlock DescriptionITM Instruction TLB MissICM Instruct

CHAPTER 2 VR4120A96Preliminary User’s Manual S15543EJ1V0UM2.3.5.1 Exception conditionsWhen an exception condition occurs, the relevant instructio

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM972.3.5.2 Stall conditionsStalls are used to stop the pipeline for conditions detected af

CHAPTER 2 VR4120A98Preliminary User’s Manual S15543EJ1V0UM2.3.5.3 Slip conditionsDuring Φ2 of the RF stage and Φ1 of the EX stage, internal logic

CHAPTER 2 VR4120APreliminary User’s Manual S15543EJ1V0UM99Figure 2-24. MD Busy Interlock1MFLO/MFHIBypassDetect MD busy interlockIF RF EX DC WBIF